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ML5800
5.8GHz Low-IF 1.5Mbps FSK Transceiver FINAL Datasheet
GENERAL DESCRIPTION
The ML5800 is a high integration 5.8GHz Frequency Shift Keyed (FSK) transceiver that integrates all frequency generation, receive, and transmit functions required to realize a digital cordless telephone. Only a power amplifier (PA) and antenna switch are required to form a complete 5.8GHz digital radio. The ML5800 operates in the 5.725 to 5.850GHz unlicensed ISM band. It can be used to implement both Direct Sequence and Frequency Hopping Spread Spectrum radios. The ML5800 contains a dual-conversion low-IF receiver with all channel selectivity on chip. IF filtering, IF gain, and demodulation are performed on chip eliminating the need for any external IF filters or production tuning. A post detection filter and a data slicer are integrated to complete the receiver. The ML5800 transmitter uses an adjustment-free twoport closed loop modulator, which modulates the onchip VCO with filtered data. An upconversion mixer and buffer/predriver produces output of 0dBm at 5.8GHz. A fully integrated 3.9GHz fractional synthesizer is used in both receive and transmit modes. Power supply regulation is included in the ML5800, providing circuit isolation and consistent performance over supply voltages between 2.7V-3.6V.
FEATURES
High Integration 5.8GHz FSK Transceiver High data rate - 1.536Mbps Low-IF receiver eliminates external IF filters Fully integrated IF filters, FM discriminator, and data filters Self-calibrated filters eliminate production tuning 4dB (typ) Input-referred Noise Figure -94dBm (typ) sensitivity @ 0.1% BER 0dBm (typ) Output Power Simple 3-wire Control Interface PA sequencing & integrated pin diode driver Analog RSSI output over a 68dB range Auxiliary switch for transmit power control "Green" (Pb-Free) 32 pin LPCC package
APPLICATIONS
Digital Cordless Telephones Wireless Streaming Audio and Video Game Controllers High-speed Data Links
PIN CONFIGURATION
VCCTXMIX
Top View
VCCIF DOUT RSSI VDD DIN
GNDIF
BLOCK DIAGRAM
VCCA VCCRF GNDTX TXO RXI VCCLNA VCCRXMIX GNDMIX
Quadrature Generation PAON Mode Control Transmit Mixer TXO 5.8GHz Output Two-port Modulator Control Registers PLL Divider Ref. Divider RXON XCEN Transmit Data Input Serial Control Bus Frequenc Referenc Filter Alignment RSSI RXI 5.8GHz Input Receiver Mixer Quadrature Downmixers F to V DOUT Digital Output
XCEN RXON PAON EN DATA CLK AOUT_TPC VSS
PIN 1
VBG
AOUT_TPC Analog Output RSSI Receive Signal Strength Indicator Control lines
VCCPLL
GNDPLL
VCCB
VCCVCO
VTUNE
FREF
QPO
GNDLO
DIN DATA CLK EN FREF
ORDERING INFORMATION
PART NUMBER TEMP RANGE ML5800DM ML5800DM-T PACKAGE PACK (QTY) -10oC to +60oC 32 LPCC 5x5 mm Antistatic Tray (490) -10oC to +60oC 32 LPCC 5x5 mm Tape & Reel (2500)
3.9 GHz VCO P.D.
VTUNE
QPO PLL Loop Filter
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TABLE OF CONTENTS
GENERAL DESCRIPTION ........................................................................................................................................... 1 PIN CONFIGURATION ................................................................................................................................................. 1 ORDERING INFORMATION ........................................................................................................................................ 1 FEATURES ................................................................................................................................................................... 1 APPLICATIONS ............................................................................................................................................................ 1 BLOCK DIAGRAM ........................................................................................................................................................ 1 TABLE OF CONTENTS ................................................................................................................................................ 2 ELECTRICAL CHARACTERISTICS............................................................................................................................. 3 PIN DESCRIPTIONS.................................................................................................................................................... 5 MODES OF OPERATION........................................................................................................................................... 12 CONTROL INTERFACES........................................................................................................................................... 14 TRANSMIT & RECEIVE DATA INTERFACES............................................................................................................ 17 REGISTER DESCRIPTIONS ..................................................................................................................................... 18 PHYSICAL DIMENSIONS .......................................................................................................................................... 24 WARRANTY................................................................................................................................................................ 25
SIMPLIFIED APPLICATIONS DIAGRAM
TPC DOUT 32 3 PAON ANTENNA PAON AOUT_TPC 7 RSSI 28 DOUT AOUT RSSI FREF CLK, DATA, EN 3 B ASE B AND IC XCEN, 2 RXON
ML5800
FREF 9 DATA 5 CLK 6 EN 4
RXI T/R SWITCH
20 RXI
RXON 2 XCEN 1
TXO
21 TXO
VTUNE 15
DIN 30 VCCA 24 QPO VDD 11 31
DIN VCCA VDD BATTERY AND PROTECTION CIRCUITS
PA - M L 5803
VTUNE QPO
14 VCCVCO
Figure 1: Simplified ML5800 Application Diagram
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ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Operating the device for any length of time beyond the operating conditions may degrade device performance and/or shorten operating lifetime. VCCA, VDD ...............................................................................................................................................VSS-0.3 to 3.6V Junction Temperature............................................................................................................................................... 150C Storage Temperature Range ...................................................................................................................... -65C to 150C Lead Temperature (Soldering, 10s).......................................................................................................................... 260C
OPERATING CONDITIONS
Ambient Temperature Range (TA) ............................................................................................................... -10C to 60C VCCA Range ...................................................................................................................................................2.7V to 3.6V VDD Range .....................................................................................................................................................2.7V to 3.6V Thermal Resistance (JA)....................................................................................................................................... 36C/W Maximum receive RF input power .........................................................................................................................-10dBm Unless otherwise specified data is over operating conditions (TA = -10C to 60C, VCCA = VDD = 2.7V to 3.6V ) and fREF = 6.144MHz, V23PLL=0, at Freq=5779.456MHz (N=229, P=0). Typical defined as VCCA = VDD = 3.3V, TA = 25C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES VCCA VDD VBG VREG VVCO ISTBY IRX ITX Analog supply voltage Digital supply voltage Bandgap Voltage Regulated Voltage VCO Regulated Voltage Supply current, STANDBY mode Supply current, RECEIVE mode Supply current, TRANSMIT mode VDD pin (VCCA VDD always) VBG(p26), IO=0A VCCPLL(p10), VCCRF(p23), VCCTXMIX(p27), VCCIF(p29), IO=0A VCCVCO(p14), IO=0A, VCCB(p13)=2.7V DC supply connected, XCEN low, 25C and 3.0V RX chain active, data being received POUT=0dBm 2.7 2.7 3.3 3.3 1.23 2.7 2.5 0.1 65 60 90 80 3.6 VCCA V V V V V A mA mA
SYNTHESIZER fC f IP N Carrier frequency range Channel Spacing Charge Pump sink/source current Phase noise at driver output fo=1.2MHz offset from fc fo=3MHz offset from fc fo>7MHz offset from fc tFH Lock time for channel switch (2.560MHz channels) From EN asserted to RX valid data (RX), or PAON high (TX) 1 Channel 5 Channels Full Range tTX2RX Lock time for TX/RX RXON High to Valid RX data 110 185 250 70 s s s s -90 -110 -120 dBc/Hz dBc/Hz dBc/Hz 0.22 5.725 512kHz Steps 0.52 1.2 mA 5.850 GHz
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SYMBOL tRX2TX tWAKE fFREF VFREF RECEIVER Zin, S11 NF GRX DRRX S BWRX PIMAX IIP3 PRXI IRR ACR Input Impedance Input noise figure RX Gain Data Rate Input Sensitivity RX Data Filter 3dB Bandwidth Maximum RX RF input RX RF input IP3 LO leakage at RXI RX Chain Image rejection ratio RX adjacent channel(s) rejection. 2.56MHz channel spacing Wanted at -80dBm 1 channel 2 channels 3 or more channels RECEIVE LOW IF FILTERS fIFC BWIFC IF filter center frequency IF filter 3dB bandwidth Post-alignment Post-alignment 1.024 1.408 MHz MHz 15 40 45 dB dB dB <0.1% BER Gaussian 5 order <0.1% BER at 1.536Mbit/sec Test tones 2 and 4 channels away At 5.8GHz 35
th
PARAMETER Lock time for RX/TX Lock up time from standby Reference signal frequency Reference signal input level
CONDITIONS RXON Low to PAON high XCEN high to Valid RX data, XCEN low period >120 seconds
MIN
TYP 62.5 275 6.144 12.288
MAX
UNITS s s MHz MHz
6.144MHz or 12.288MHz sine wave, capacitively coupled
2.0
VCCA
VP-P
at RXI 5.725-5.850GHz at RXI 5.725-5.850GHz, RXI to Limiter
24.5+j28
dB dB Mbps dBm kHz dBm dBm -50 dBm dB
4.0 80 1.536 -94 768 -10 -27
LIMITER, AGC, AND FM DEMODULATOR tOVLD Recovery from overload Transition time to switch from Pin = - 10dBm input to Pin = -90dBm, time to valid RX data Wanted at CHx -80dBm, unwanted at CHx modulated with 1.536Mbps GFSK, BT=0.5, PRBS data 20 s
Co-Channel rejection, 0.1% BER
-20
dB
VODC VOPK RSSI tR_RSSI tF_RSSI VRSMX VRSMD VRSMN VRSMXC GRSSI
Quiescent output voltage @ AOUT_TPC(pin 7), AOUT Mode Output voltage swing AOUT_TPC(pin 7), AOUT Mode
1.15 0.8
V VP-P
RSSI rise time. < -100dBm to -15dBm into the RF mixer RSSI fall time. -15dBm to < -100dBm into the IF mixer RSSI maximum voltage RSSI midrange voltage RSSI minimum voltage RSSI maximum voltage (clipped) RSSI sensitivity RSSI accuracy
20pF loading on the RSSI output. Rise time from 20% to 80% 20pF loading on the RSSI output. Fall time from 80% to 20% -10dBm into RXI -40dBm into RXI No signal applied -10dBm into RXI (V-40dBm - V-50dBm)/10dB Deviation from best fit straight line
5 5 2.7 2.5 0.2 2.3 35 3
s s V V V V mV/dB dB
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TRANSMITTER Zout S22 POUT Output Impedance TX buffer output power at 5.8GHz at TXO Matched into 50ohms, 25C and 3.3V Matched into 50ohms, over operating temperature and voltage range fDEV BWTX PSPUR PIMAGE Transmit Modulation Deviation TX Data Filter 3dB Bandwidth TX spurious TX Image 2/3 FTXO, 1/3 FTXO TXO pin See Figure 6 -4 -7 22.5+j3 0 0 512 1.4 -25 -20 3 3 kHz MHz dBc dBc dBm
INTERFACE LOGIC LEVELS Input pins (DIN, XCEN, RXON, DATA, CLK, EN) VIH VIL IB CIN Input high voltage Input low voltage Input bias current Input capacitance All states 1MHz test frequency VDD*0.7 -0.4 -5 4 VDD+0.4 VDD*0.3 5 V V A pF
Output pins (AOUT_TPC, PAON, DOUT) VOL VOH VOL Io VOH VOL AOUT open-drain voltage PAON (PA control) output high voltage PAON (PA control) output low voltage PAON source/sink current DOUT (data output) output high voltage DOUT (data output) output low voltage Sourcing 0.1mA Sinking 0.1mA IO=100A, TPC Mode Sourcing 5.0mA Sinking 5.0mA 5.0 VDD-0.4 0.4 8.0 VDD-0.4 0.4 0.4 V V V mA V V
3 WIRE SERIAL BUS TIMING tr tf tck tew tl tse ts th CLK input rise time (note 1) CLK input fall time (note 1) CLK period EN pulse width Delay from last clock rising edge to rise of EN EN setup time to ignore next rising CLK DATA-to-CLK setup time DATA-to-CLK hold time 50 200 15 15 15 15 See Figure 5 15 15 ns ns ns ns ns ns ns ns
Note 1: Serial I/O clock maximum rise and fall times are based on the minimum clock period. Longer rise and fall times can be accommodated for slower clocks provided the rise and fall times remain less than 20% of the clock period and all set up and hold time minimums are met with respect to the CMOS switching points (VIL MAX and VIH MIN). The serial I/O clock rise and fall times are limited to an absolute maximum of 100ns.
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PIN DESCRIPTIONS
PIN SIGNAL NAME I/O FUNCTION DIAGRAM
POWER & GROUND
8 10 VSS VCCPLL GND PWR/O (Decouple only) Digital Ground. Ground for digital I/O circuits and control logic. PLL Supply. DC power supply decoupling point. This pin is connected to the output of the regulator and to the PLL supplies. A capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. Ground for the PLL. Regulated DC Power Supply Input to the VCO voltage regulator. Must be connected to VCCIF (pin 29) via decoupling network. DC power supply decoupling point for the VCO. Connected to the output of the VCO regulator. A capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. DC ground for VCO and LO circuits. Ground for exposed die paddle. Regulated RX mixer DC supply input. A capacitor must be tied between this pin and ground to decouple (bypass) noise. Must be connected to VCCTXMIX (pin 27). N/A See Pin 11 below.
12 13
GNDPLL VCCB
GND PWR/I (Regulated Input)
N/A N/A
14
VCCVCO
PWR/O (Decouple only)
N/A
16 N/A 18
GNDLO GNDDB VCCRXMIX
GND GND PWR/I (Regulated Input)
N/A See Pin 20 below N/A
19
VCCLNA
PWR/I (Regulated Input)
Regulated DC Power supply input to the LNA. A capacitor must be tied between this pin and ground to decouple (bypass) noise. Must be connected to VCCTXMIX (pin 27).
N/A
17 22 23
GNDMIX GNDTX VCCRF
GND GND PWR/O (Decouple only)
Signal ground for the receive mixers. Signal ground for the transmitter. DC power supply decoupling point for the LO chain. Connected to the output of a regulator. A capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. Unregulated DC power supply input to voltage regulators and unregulated loads: 2.7 to 3.6V. VCCA is the main (or master) analog VCC pin. There must be capacitors to ground from this pin to decouple (bypass) supply noise. DC ground to IF circuits. Bandgap decouple voltage. Decoupled to ground with a capacitor. DC power supply output and decoupling point for TX mixer regulator. A capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator.
N/A N/A N/A
24
VCCA
PWR/I (Unregulated Input)
N/A
25 26
GNDIF VBG
GND PWR/O (Decouple only)
N/A N/A
27
VCCTXMIX
PWR/O (Regulated Output)
N/A
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29 VCCIF PWR/O (Regulated Output) 31 VDD PWR/I (Unregulated Input) DC power supply output and decoupling point for the IF regulator. A capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. DC digital power supply input to the interface logic and control registers. This supply is not connected internally to any other supply pin, but its voltage must be less than or equal to the VCCA supply and greater than or equal to 2.7V. A capacitor must be tied between this pin and ground to decouple (bypass) noise. N/A
N/A
TRANSMIT/RECEIVE
20 RXI I (Analog) Receive RF Input. A simple matching network is required for optimum noise figure. This input connects to the base of an NPN transistor and should be AC coupled.
RXI 20 VCCA 24 0.7V
4k
VSS (PIN 8) VCCA (PIN 24)
GNDDB
8 VSS
21
TXO
O (Analog)
TX RF open-collector output. 0dBm nominal output power into a matched load over 5.725 to 5.850GHz range. This output requires a DC path to VCCA.
TXO
21
GNDDB
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DATA
7 AOUT_TPC O (Analog) Multi-function Output. In Analog output mode this output drives an off chip data slicer. In Transmit power control mode this is an open drain output, which is pulled low when the TPC bit (R0:B7) is set to 0. Transitions on TPC are synchronized to the falling edge of RXON (Rx to Tx transition).
TPQ MUX
VDD 31
TPC
TPC MUX
7
AOUT
100
8 VSS
8 VSS
AOUT MUX
30
DIN
I (CMOS)
Transmit Data Input. Drives the transmit pulse shaping circuits. Serial digital data on this pin becomes FSK modulation on the Transmit RF output. The logic timing on this pin controls data timing. Internal circuits determine the modulation deviation. This is a standard CMOS input referenced to VDD and VSS. Serial digital output after demodulation, chip rate filtering and center data slicing. A CMOS level output (VSS to VDD) with controlled slew rates. A low drive output designed to drive a short PCB trace and a CMOS logic input while generating minimal RFI. The internal data slicer is limited to 0 or 1 run lengths of less than 3uS.
See Pin 1 below.
32
DOUT
O (CMOS)
VDD 31
250
32 DOUT
8
VSS
MODE CONTROL AND INTERFACE LINES
1 XCEN I (CMOS) Transceiver enable input. Enables the bandgap reference and voltage regulators when high. Consumes only leakage current in STANDBY mode when low. This is a CMOS input, and the thresholds are referenced to VDD and VSS. TX/RX Control Input. Switches the transceiver between TRANSMIT and RECEIVE modes. Circuits are powered up and signal paths reconfigured according to the operating mode. This is a CMOS input, and the thresholds are referenced to VDD and VSS.
VDD 31
XCEN
1
2
RXON
I (CMOS)
RXON
2
DIN
30
8 VSS
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3 PAON O (CMOS) PA Control Output. Enables the off-chip PA at the correct times in a Transmit slot. Goes high when transmit RF is present at TXO; goes low 5s before transmit RF is removed from TXO. This output has 5mA drivers suitable for driving pin diode switches directly. It also has optional interlock logic to disable the PA when the PLL is out of lock.
VDD 31
3
PAON
8
VSS
9
FREF
I (Analog)
Input for the 12.288MHz or 6.144MHz reference frequency. This input is used as the reference frequency for the PLL and as a calibration frequency for the on-chip filters. An AC-coupled sine or square wave source drives this self-biased input. The reference source must be accurate to 20 PPM.
VCCA 24
9 FREF
40k
40k
8 VSS
11
QPO
O (Analog)
Charge Pump Output of the phase detector. This is connected to the external PLL loop filter.
VCCPLL 10
11 QPO
8 VSS
15
VTUNE
I (Analog)
VCO Tuning Voltage input from the PLL loop filter. This pin is very sensitive to noise coupling and leakage currents.
VCCB 13
2.5V
VTUNE
15
3.7k
8 VSS
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28 RSSI O (Analog) Buffered analog RSSI output with a nominal sensitivity of 35mV/dB.
TPI MUX
VCCA 24
RSSI RSSI MUX 28 RSSI
OP AMP
100
8 VSS
SERIAL BUS SIGNALS
4 EN I (CMOS) Control Bus Enable. Enable pin for the threewire serial control bus that sets the operating frequency and programmable options. The control registers are loaded on a low-to-high transition of the signal. Serial control bus data is ignored when this signal is high. This is a CMOS input, and the thresholds are referenced to VDD and VSS. Serial Control Bus Data. 16-bit words, which include programming data and the two-bit address of a control register. This is a CMOS input, and the thresholds are referenced to VDD and VSS. Serial control bus data is clocked in on the rising edge when EN is low. This is a CMOS input; the thresholds are referenced to VDD and VSS.
VDD 31
EN
4
5
DATA
I (CMOS)
5.5k
DATA 5 CLK 6 8 VSS
1.7p
6
CLK
I (CMOS)
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FUNCTIONAL DESCRIPTION
The ML5800 enables the design and manufacture of low-cost, small yet high-performance digital RF transceivers in the relatively interference-free 5.8GHz ISM band. Frequency Shift Keying (FSK) is a constant-envelope modulation, which allows the use of high-efficiency class C power amplifier (such as the ML5803) resulting in longer battery life. Integrated in the ML5800 is a dual-conversion low-IF receiver with completely integrated filters, all frequency generation circuits, and transmit circuits. On-chip regulators protect critical circuits from power-supply noise and allow for consistent performance over the supply voltage range. The ML5800 transmits and receives 1.536Mbps FSK data in the 5.725 to 5.850GHz ISM band. The high data rate allows for direct sequence spread spectrum coding, which increases interference rejection and input sensitivity at the cost of reduced effective data rate. For example, a 15-chip spreading sequence results in 11.7dB of processing gain and a `raw' data rate of 102.4kbps. The ML5800 contains a dual-conversion low-IF receiver. The first IF frequency of 1.9GHz gives an image response, also at 1.9GHz. An off-chip filter is needed to protect the receiver from this image and from IF feedthrough. The second IF frequency of 1.024MHz results in an image response in an adjacent channel. The quadrature image-reject mixer and low IF filter combine to achieve a typical image rejection of 35dB. All IF filtering and demodulation are performed on chip using active filtering, centered at 1.024MHz. A matched bit-rate filter and data slicer follow the demodulator and provide sliced data at the DOUT pin. Buffered analog (unsliced) data is available on the AOUT_TPC pin. The ML5800 transmitter uses a fractional-N PLL and two-port closed loop modulation to accurately impress the FSK signal on the 5.8GHz carrier. Closed loop modulation techniques allow for continuous transmission or reception of data without significant frequency drift, making the ML5800 ideal for wireless streaming media applications. A lock-detect circuit monitors the state of the PLL loop. When the PLL is out of lock the transmitter output is disabled. The frequency generation circuits are comprised of a fully integrated 3.9GHz VCO local oscillator (LO), dividers, a phase comparator, and a charge pump for a PLL frequency synthesizer. A fractional-N PLL applies the low frequency data modulation onto the LO. The LO is halved to generate accurate quadrature signals at 1.9GHz for the second LO. The LO PLL is programmed via the three-wire serial bus (CLK, DATA, EN). There is no error checking of the program data. This bus is functional, and register contents are preserved in STANDBY mode.
Receiver Mixer RXI 5.8GHz Input Quadrature Downmixers F to V DOUT Digital Output
Filter Alignment
AOUT_TPC Analog Output RSSI RSSI Receive Signal Strength Indicator Control lines
Quadrature Generation PAON Mode Control Transmit Mixer TXO 5.8GHz Output Two-port Modulator Control Registers PLL Divider Ref. Divider RXON XCEN
DIN DATA CLK EN FREF
Transmit Data Input Serial Control Bus Frequenc Referenc
3.9 GHz VCO P.D.
VTUNE
QPO PLL Loop Filter
Figure 2: ML5800 Block Diagram
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MODES OF OPERATION
The ML5800 has three key modes of operation:
STANDBY: RECEIVE: TRANSMIT:
All circuits powered down, except the control interface (static CMOS) Receiver circuits active Transmitter circuits active
MODE CONTROL
The two modes of operational are RECEIVE and TRANSMIT, controlled by RXON. XCEN is the chip enable/disable control pin, which sets the device in operational or STANDBY modes. The relationship between the parallel control lines and the mode of operation of the IC is summarized in Table 1.
XCEN
0 1 1
RXON
X 1 0
MODE NAME
STANDBY RECEIVE TRANSMIT
FUNCTION
Control interfaces active, all other circuits powered down Receiver time slot Transmit time slot
Table 1: Modes of Operation
STANDBY MODE
In STANDBY mode, the ML5800 transceiver is powered down. The only active circuits are the control interfaces, which are static CMOS to minimize power consumption. The serial control interface and control registers remain powered up and will accept and retain programming data as long as the VDD and VCCA are present. When exiting STANDBY mode, remain in RECEIVE mode for at least 62.5s (typ) to allow for filter calibration.
RECEIVE MODE
In RECEIVE mode, the received signal at 5.8GHz is down converted, bandpass filtered (IF filter), fed to the frequencyto-voltage converter, and low-pass filtered. The output of the low-pass filter is available at both the AOUT_TPC pin and to the on-chip data slicer, which outputs NRZ digital data to the DOUT pin. An RSSI voltage output indicates the RF input signal level at the output of the IF filter.
Receive Signal Strength Indication (RSSI)
RSSI is an indication of field strength. It can be used by the system to determine transmit power control (conserve battery life) and/or to determine if a given channel is occupied.
Automatic Filter Alignment
When the chip is powered up the tuning information is reset to mid-range. In the first 62.5s of RECEIVE mode (RXON set high) the ML5800 performs filter self-calibration, which tunes all the internal filters relative to the signal on the FREF pin. Valid data is received after calibration is completed. Self-calibration sets: Discriminator center frequency IF filter center frequency and bandwidth Receiver data low-pass filter bandwidth Transmit data low-pass filter bandwidth
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TRANSMIT MODE
In TRANSMIT mode, the PLL loop is closed to eliminate frequency drift. A two-port modulator modulates both the VCO and the fractional-N PLL. The VCO is directly modulated with filtered FSK transmit data. The PLL is driven by a sigmadelta modulator, which ensures that the PLL follows the mean frequency of the modulated VCO.
PLL Programming & Channel Selection
The ML5800 PLL is programmed with a 14bit word to set the RF center frequency of the radio. The channel frequency (fc) is given by:
fc = 1.5 * 6.144 * (512 +N/2 + (P+11)/18) MHz
Where N is the "integer" portion and P is the "fractional" portion of the synthesizer. See Register 1 Description for further details on how to program the channel frequency plan in the control register.
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CONTROL INTERFACES
There are two sets of control interfaces for the ML5800:
RF Control: Serial Bus Control:
XCEN, RXON, FREF, RSSI, PAON, AOUT_TPC EN, DATA, CLK
The ML5800 transceiver is used in time division duplex (TDD) mode, where the transceivers at each end of a radio link alternately transmit and receive. Immediately before data is transmitted or received the ML5800 goes through a `selfcalibration' sequence, where the IF and data filters are frequency aligned while the PLL settles to the carrier frequency. These calibration cycles are triggered by logic transitions on the control interface. Figure 3 shows the normal operating cycle for the ML5800.
XCEN
tWAKE tMAX
tRX2TX
tMAX
tED
tTX2RX
RXON
PAON
AOUT_TPC
DIN
Tx Data
DOUT
Valid RX Data
TXO
Figure 3: Control Timing for TDD Operation
To implement channel scanning, the ML5800 is kept in RECEIVE mode (XCEN and RXON high) and the PLL is reprogrammed to select a different RF channel. A filter calibration cycle is initiated by each serial bus write to the register controlling the PLL modulus, so that filter alignment is updated as the VCO settles to the next programmed channel frequency. Serial bus writes to other registers do not trigger a calibration cycle. Signal diagram for channel scanning is shown in Figure 4.
XCEN
tWAKE
tFH
EN (Write to PLL tuning register)
DOUT
Valid RX Data
Valid RX Data
Figure 4: Control Timing when Channel Scanning
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Table 2 gives the minimum times between transitions on the control interface for the ML5800 transceiver to work correctly. Times t1, t2, and t4 are the minimum delays that the baseband design must allow before valid receive data is expected on the DOUT pin.
SYMBOL
tWAKE tFH tTX2RX tRX2TX tMAX tED
PARAMETER
Wait time from XCEN asserted to valid Receive data out Time from rising edge of Serial Bus EN to valid Receive data out (channel scan mode, one channel hop, PLL re-locking triggered by rising EN). Time from rising edge of RXON to valid Receive data out Time from falling edge on RXON to start of valid data on DIN pin. Note that RF energy will be present on TXO during this period but PAON will be unasserted. Maximum TX or RX time under steady state operating temperatures (<2C/minute) Time from rising edge on RXON to end of valid data on DIN pin (Start of PLL Freq. shift)
WORST CASE TIMING
325 125 120 62.5 60 6
UNITS
s s s s s s
Table 2: Transceiver Control Interface Timing
RF CONTROL: XCEN, RXON, FREF, RSSI, PAON & TPC
The XCEN pin enables/disables the ML5800 and places the device in either standby or active modes. The default power up is in RECEIVE mode. The RXON pin determines which active mode the ML5800 is in: RECEIVE or TRANSMIT. The FREF pin is the master reference frequency for the transceiver. It supplies the frequency reference for the RF channel frequency and the on-chip filter tuning. The FREF pin is a CMOS input with on-chip biasing resistors. It can be driven by an AC coupled sine-wave source or by a CMOS logic output. FREF is used as a calibration frequency and as a timing reference in the control circuits. The reference source must be accurate to 20 PPM. The RSSI pin supplies a voltage that indicates the amplitude of the received RF signal. It is connected to the input of a low-speed ADC on the baseband IC, and is used during channel scanning to detect clear channels on which the radio can transmit. The RSSI (Received Signal Strength Indicator) voltage is proportional to the logarithm of the received power level. The ML5800 has two output pins that control and sequence the power amplifier (PA): PAON and AOUT_TPC. The PAON (PA control) is a 5mA CMOS output that controls an off-chip RF PA and T/R switch (can directly drive PIN diodes). It outputs a logic high when the PA should be enabled and a logic low at all other times. This output is inhibited when the PLL fails to lock. When digital data output (DOUT) is used, the AOUT_TPC pin is an open-drain output intended for transmit power control (TPC). It is configured by Bit 4 in Register 0 (AOUT) and when selected as a TPC output, reflects the state of Bit 7 in Register 0 (TPC). The TPC register bit can be changed at any time, but the AOUT_TPC pin does not change state until the beginning of the next transmit slot, triggered by a falling edge on RXON. In analog data output mode, the AOUT_TPC pin becomes the analog data output to an off-chip data slicer.
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ML5800
SERIAL BUS CONTROL: EN, DATA, CLK
A 3-wire serial interface is used for programming the ML5800 configuration registers, which control device mode of operation, pin functions, PLL and reference dividers, internal test modes and filter alignment. Data words are entered beginning with the MSB. The word is divided into a leading 14-bit data field followed by a 2-bit address field. When the address field has been decoded the destination register is loaded on the rising edge of EN. Providing less than 16 bits of data will result in unpredictable behavior when EN goes high. Data and clock signals are ignored when EN is high. When EN is low, data on the DATA pin is clocked into a shift register by rising edges on the CLK pin. The information is loaded into the addressed latch when EN returns high. This serial interface bus is an industry standard bus commonly found on PLL devices. It can be efficiently programmed by either byte or 16-bit word oriented serial bus hardware. The data latches are implemented in CMOS and use minimal power when the bus is inactive. See Figure 5 and Table 3.
tf th tr
ts
tck tl
CLK Data
MSB
tse
tew EN
Figure 5: Serial Bus Timing Diagram
SYMBOL
PARAMETER
MIN
MAX
UNITS
BUS CLOCK (CLK) tr tf tck Clock input rise time (note 1) Clock input fall time (note 1) Clock period 50 15 15 ns ns ns
ENABLE (EN) tew tl tse Minimum pulse width Delay from last clock rising edge to rise of EN Enable set up time to ignore next rising clock 200 15 15 ns ns ns
BUS DATA (DATA) ts th Data to clock set up time Data to clock hold time 15 15 ns ns
Table 3: Serial Bus Timing Specifications
Note 1: Serial I/O clock maximum rise and fall times are based on the minimum clock period. Longer rise and fall times can be accommodated for slower clocks provided the rise and fall times remain less than 20% of the clock period and all set up and hold time minimums are met with respect to the CMOS switching points (VIL MAX and VIH MIN). The serial I/O clock rise and fall times are limited to an absolute maximum of 100ns.
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ML5800
TRANSMIT & RECEIVE DATA INTERFACES
There are two sets of transmit and receive data interfaces for the ML5800:
Baseband Data: RF Data:
DIN, DOUT, AOUT RXI, TXO
BASEBAND DATA: DIN, DOUT, AOUT
The DIN pin is a CMOS-level serial data input for FSK modulation on the radio channel. This DIN pin drives data bits into the two-port transmit modulator. When used with Direct Sequence Spread Spectrum (DSSS), the chip rate, bit rate and spreading code are determined in the baseband processor and the FM deviation and transmit filtering are determined in the ML5800. There is no re-timing of the chips, so the transmitted FSK chips take their timing from the data on this pin. The DOUT pin is a corresponding CMOS-level digital data output. The data on this pin is valid only when the run length of the transmitted digital data is limited to consecutive 1's or 0's no longer than 3s. When longer run lengths are used, an off-chip data slicer is required, driven from the AOUT_TPC pin. Setting the AOUT bit in Register 0 turns the AOUT_TPC pin into a buffered, single-ended analog output from the data filter. This output can be used to drive an off-chip data slicer or an ADC input for a DSP data slicer. Clock recovery for both DOUT and AOUT modes is performed in the baseband.
RF DATA: RXI, TXO
The RXI receive input (pin 20) and the TXO transmit output (pin 21) are the only RF I/O pins. The RXI pin requires a simple impedance matching network for best input noise figure, and the TXO pin also requires a matching network for maximum power output into 50. The voltage on the modulation port swings above and below its central value to produce 2-FSK modulation on the VCO (See Figure 6). For best performance, all RF ground pins must have a direct connection to the RF ground plane, and the RF supply pins must be well decoupled from the RF ground pins.
FMAX FMIN FDEV
FOS
TRANSIENT TRANSMIT MODULATION
NAME FDEV FMAX FMIN FOS DESCRIPTION Final Modulation Deviation Maximum Modulation Deviation Minimum Modulation Deviation Modulation center frequency offset
Freq=5.779456GHz, VCCA=VDD=3.3V, Ta=25C
MIN 500 TYP 512 720 450 50 MAX 524 Units kHz kHz kHz kHz
CONDITIONS After 200us of consecutive 1 or 0 bits PN (15 bit) Sequence Encoded Data @ 1.536Mb/s PN (15 bit) Sequence Encoded Data @ 1.536Mb/s 50us after RXON low
Figure 6. Transient Transmit Modulation Waveform
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ML5800
REGISTER DESCRIPTIONS
A 3-wire serial data input bus sets the ML5800's transceiver parameters and programs the PLL circuits. Entering 16-bit words into the ML5800 serial interface performs programming. Three 16-bit registers are partitioned such that 14 bits are dedicated for data to program the operation and two bits identify the register address. The contents of these registers cannot be read back. The three registers are:
Register 0: PLL Configuration Register 1: RF Channel Frequency Configuration Register 2: Test Mode Access Figure 7 shows a register map. Table 4 through Table 21 provide detailed diagrams of the register organization: Table 4 outlines the PLL configuration register (Register 0), Table 17 describes the channel frequency register (Register 1), and displays the filter tuning and test mode register (Register 2).
MSB DB13 Res. B15 DB12 Res. DB11 DB10 DB9 DB8 DB7 DB6 TXM B8
Data
DB5 TPC B7 DB4 TXCW B6 DB3 LOL B5 DB2 AOUT B4 DB1 RD0 B3 DB0 QPP B2
Address
ADR1 0 B1 ADR0 0 B0
NOPD RCLP LVLO TXOL V23PLL B9 B14 B13 B12 B11 B10
Register 0: PLL Configuration Register
MSB DB13 N9 DB12 N8 B15 DB11 N7 B14 DB10 N6 B13 DB9 N5 B12 DB8 N4 B11 DB7 N3 B10 DB6 N2 B9
Data
DB5 N1 B8 DB4 N0 B7 DB3 P3 B6 DB2 P2 B5 DB1 P1 B4 DB0 P0 B3
Address
ADR1 0 B2 ADR0 1 B1 B0
Register 1: RF Channel Frequency Configuration Register
MSB DB13 DB12 TMODE CFB6 B15 DB11 CFB5 B13 DB10 CFB4 B12 DB9 CFB3 B11 DB8 CFB2 DB7 CFB1 DB6 CFB0 B9
Data
DB5 DTM2 B8 B7 DB4 DTM1 B6 DB3 DTM0 B5 DB2 ATM2 B4 DB1 ATM1 B3 DB0 ATM0 B2
Address
ADR1 1 B1 ADR0 0 B0
B14
B10
Register 2: Test Mode Access Register
Figure 7: Configuration Register Map
Power-On State
On power up, all register bits are cleared to the default value of 0 (zero). Power up is defined as occurring when VDD 2.0V. The register default values are valid upon power up.
Register Format
The two least significant bits of every register are the address bits ADR <1:0>. Each register is divided into a data field and address field. The data field is the leading field, while the last two bits clocked into the register are always the address field. When EN goes high, the address field is decoded and the addressed destination register is loaded. The last 16 bits clocked into the serial bus are loaded into the register. Clocking in less than 16 bits may result in an incorrect entry into the register.
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ML5800
REGISTER 0 BIT DESCRIPTIONS
DATA BIT
B15 (MSB) / DB13 B14 / DB12 B13 / DB11 B12 / DB10 B11 / DB9 B10 / DB8 B9 / DB7 B8 / DB6 B7 / DB5 B6 / DB4 B5 / DB3 B4 / DB2 B3 / DB1 B2 / DB0 B1 / ADR1 B0 (LSB) / ADR0
NAME
Reserved Reserved V23PLL NODP RCLP LVLO TXOL TXM TPC TXCW LOL AOUT RD0 QPP ADR1 ADR0
DESCRIPTION
Reserved Reserved Low Voltage PLL Regulator No Dither RSSI Clip Enable Low Voltage Lockout Transmit PLL Mode TX RF Output Mode Transmit Power Control Transmit Test Mode PLL IF Shift Configuration Analog Output Reference Frequency Select PLL Charge Pump Polarity MSB Address Bit LSB Address Bit Set bit to 0 Set bit to 0
USE
0: PLL Regulator set to 2.7V 1: PLL Regulator set to 2.3V 0: 2 order Fractional-N 1: 1 order Fractional-N 0: RSSI hardware clipping 1: No RSSI clipping 0: PAON unaffected by low voltage events 1: PAON gated by latched low voltage lockout 0: Closed Loop in Transmit mode 1: Open Loop in Transmit mode 0: TXO always on in Transmit mode 1: TXO follows PAON signal 0: AOUT pin pulled to ground 1: AOUT pin high impedance 0: FSK modulation in Transmit mode 1: CW in Transmit mode (no modulation) 0: -1.024MHz LO Shift in Receive 1: +1.024MHz LO Shift in Receive 0: AOUT pin is Transmit Power Control 1: AOUT pin is Analog Data Out 0: 6.144MHz nominal reference frequency 1: 12.288MHz nominal reference frequency (preferred) 0: Fc < Fref; Charge pump sources current 1: Fc < Fref; Charge pump sinks current ADR1 = 0 ADR0 = 0
st nd
Table 4: Register 0 - PLL Configuration Register
QPP
Charge Pump Polarity: This bit sets the charge pump polarity to sink or source current. For a majority of applications, this bit is cleared (QPP = 0). For applications where an external inverting amplifier is in the loop filter, this bit is set to 1 to change the charge pump polarity (see Table 5).
QPP
0 1
RD0
Reference Divider: This bit sets the reference divider from the FREF pin to the reference input of the PLL phase/frequency detector (see Table 6).
RD0 REFERENCE DIVISION
1 2
NOMINAL REFERENCE FREQUENCY
6.144 MHz 12.288 MHz
PLL CHARGE PUMP POLARITY
For Fc < Fref. Charge pump sources current. For Fc < Fref. Charge pump sinks current.
0 1
Table 6. Reference Frequency Select
Table 5: PLL Charge Pump Polarity
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AOUT
Analog Output Mode: This bit changes the function of the AOUT pin between an analog data output and transmit power control (see Table 7).
AOUT
0 1
TXOL
Transmit PLL Mode: This bit is provided for testing. It disables the PLL during transmit slots so that the analog modulation path onto the VCO can be tested without the digital path through the PLL (see Table 12).
TXOL
Transmit Power Control Data Filter Analog Output 0 1 Closed Loop in TX Mode Open Loop in TX Mode
AOUT PIN FUNCTION TRANSMIT PLL MODE
Table 7: AOUT Function Select Table 12: TXOL Operation
LOL
PLL IF Shift: This bit shifts the PLL by 1.024MHz in Receive mode (see Table 8).
LOL
0 1
LVLO
Low Voltage Lock Out: The LVLO bit enables a transmit low voltage lockout latch which shuts off the transmitter by de-asserting the PAON output. This latch is set if the supply voltage drops below 2.65V and is reset when RXON goes high (see Table 13).
LVLO
0 1
PLL IF SHIFT CONFIGURATION
-1.024MHz LO Shift in Receive +1.024MHz LO Shift in Receive
PAON BEHAVIOR
PAON Undisturbed PAON de-asserted when VCCA<2.65V, Reset by RXON high
Table 8: PLL IF Shift Configuration
TXCW
Transmit Continuous Wave: This bit produces a continuous wave (CW) transmitter output for product test when RXON is low (see Table 9).
TXCW
0 1
Table 13: LVLO Operation
RCLP
RSSI Clip Enable: The RCLP bit disables the RSSI clipping circuitry. With RCLP low, the RSSI output voltage is clipped at 1.95V (see Table 14).
RCLP RSSI BEHAVIOR
RSSI output clipped RSSI output not clipped
TRANSMIT MODULATION
FSK Modulation CW - No Modulation
Table 9: Transmit Modulation Mode
0
TPC
Transmit Power Control: When the AOUT bit is low, this bit controls the state of the open-drain output pin. Although this bit can be changed at any time, the AOUT pin only changes state at the falling edge of RXON (see Table 10).
TPC
0 1
1
Table 14: RCLP Operation
NODP
PLL Dithering: This bit removes 2 order dither from the fractional-N st PLL when high, reducing the PLL to a 1 order fractional-N (see Table 15).
NODP
0 1 2
nd
nd
TPC PIN STATE
Pulled to Ground High Impedance
PLL BEHAVIOR
order Fractional-N PLL
Table 10: TPC Pin State
1st order Fractional-N PLL
TXM
Transmit Mode Bit: This bit controls the TX RF buffer state timing mode. It must be reset to 0 for normal operation (see Table 11).
TXM
0 1
Table 15: Dithering Operation
V23PLL
Voltage on PLL Regulator: This bit controls the voltage of the PLL regulator. It is set to 0 for normal operation. (see Table 17).
V23PLL
0 1
TXO BUFFER BEHAVIOR
RF Output Always On in TX Mode RF Output Follows PAON
REGULATOR BEHAVIOR PLL Regulator set to 2.7V PLL Regulator set to 2.3V
Table 11: TXM Mode
Table 16: V23PLL Mode
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ML5800
REGISTER 1 BIT DESCRIPTIONS
DATA BIT
B15 (MSB) / DB13 B14 / DB12 B13 / DB11 B12 / DB10 B11 / DB9 B10 / DB8 B9 / DB7 B8 / DB6 B7 / DB5 B6 / DB4 B5 / DB3 B4 / DB2 B3 / DB1 B2 / DB0 B1 / ADR1 B0 (LSB) / ADR0
NAME
N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 P3 P2 P1 P0 ADR1 ADR0
DESCRIPTION
USE
PLL Integer Part - N
N = MOD [Floor ((F/4.608) - 0.512 - ((P+11)/18)), 1024]
PLL Fractional Part - P
P= MOD [Round (F/0.512 - 11), 9]
MSB Address Bit LSB Address Bit
ADR1 = 0 ADR0 = 1
Table 17: Register 1 - Channel Frequency Register
This register sets the channel frequency for the ML5800 transceiver. The "N" Field is the 10-bit integer part of the division ratio, modulo 1024. There is an implicit MSB in the "B16" position which is fixed to "1". Values from 0 (00 0000 0000b) to 1022 (11 1111 1110b) are all valid and correspond to N =1024 to N = 2046. The 4-bit "P" field is the fractional part of the division ratio, modulo 9. Values from 0 (0000b) to 8 (1000b) are valid. The relationship between N and P with a given channel frequency F is:
F = 1.5 * 6.144 * (512 +N/2 + (P+11)/18) MHz
To calculate N and P from the channel frequency, F (in MHz) use these formulae:
N = MOD [Floor ((F/4.608) - 0.512 - ((P+11)/18)), 1024]
P= MOD [Round (F/0.512 - 11), 9]
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ML5800
REGISTER 2 BIT DESCRIPTIONS
DATA BIT
B15 (MSB) / DB13 B14 / DB12 B13 / DB11 B12 / DB10 B11 / DB9 B10 / DB8 B9 / DB7 B8 / DB6 B7 / DB5 B6 / DB4 B5 / DB3 B4 / DB2 B3 / DB1 B2 / DB0 B1 / ADB1 B0 (LSB) / ADB0
NAME
TMODE CFB6 CFB5 CFB4 CFB3 CFB2 CFB1 CFB0 DTM2 DTM1 DTM0 ATM2 ATM 1 ATM 0 ADR1 ADR0
DESCRIPTION
USE
Filter Alignment Control Bits
See Table 21
Digital Test Control Bits
See Table 20
Analog Test Control Bits
See Table 19
MSB Address Bit LSB Address Bit
ADR1 = 1 ADR0 = 0
Table 18: Register 2 - Test Mode Access Register
ATM<2:0>
Analog Test Control Bits: The performance of the ML5800 is not specified in these test modes. Although primarily intended for IC test and debug, they also can help in debugging the radio system. The default (power-up) state of these bits is ATM<2:0> = <0,0,0>. When a non-zero value is written to the field, the RSSI and AOUT_TPC pins become analog test access ports, giving access to the outputs of key signal processing stages in the transceiver. During normal operation, the ATM field must be set to zero (see Table 19).
ATM2
0 0 0 0 1 1 1 1
ATM1
0 0 1 1 0 0 1 1
ATM0
0 1 0 1 0 1 0 1
RSSI
RSSI Data Filter input + I IF Filter Output Q IF Filter - Input I IF Filter - Input Data Filter + Output I IF Limiter Output 1.67V Voltage Reference
AOUT
Set by AOUT bit Data Filter input Q IF Filter Output Q IF Filter + Input I IF Filter + Input Data Filter -Output Q IF Limiter Output VCO Modulation Port Input
Table 19: Analog Test Control Bits
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ML5800
DTM <2:0>
Digital Test Control Bits: The performance of the ML5800 is not specified in these test modes. Although primarily intended for IC test and debug, they also can help in debugging the radio system. The default (power up) state of these bits is DTM<2:0> = <0,0,0>. When a non-zero value is written to these fields, the DOUT and PAON pins become a digital test access port for key digital signals in the transceiver. During normal operation, the DTM field must be set to zero (see Table 20).
DTM2
0 0 0 0 1 1 1 1
DTM1
0 0 1 1 0 0 1 1
DTM0
0 1 0 1 0 1 0 1
nd
PAON
PA Control No Output Prescaler Out Divide 64 No Output PLL 2 Carry Diagnostic o/p No Output 3MHz from PLL No Output
DOUT
Data Out AGC Switch State PLL Main Divider Output PLL Reference Divider Output PLL 1 Carry Diagnostic o/p TCAL (Cal. Timer) LOCKN UDLATCH
st
Table 20: Digital Test Control Bits
TMODE and CFB <6:0>
The TMODE bit disables the automatic filter alignment circuitry, and then the CFB field directly tunes the filter. The CFB field is a 7 bit binary value that tunes the IF and data filters. The correct value for CFB6 to CFB0 varies depending upon absolute values of the integrated resistors and capacitors on the chip. The IF filter center frequency, IF filter bandwidth, data filter bandwidth and F to V converter center frequency are all tuned together by the CFB field (see Table 21).
TMODE
0 1
FILTER ALIGNMENT MODE
Filters auto aligned during receive slots Filters tuned by CFB<6:0> value
Table 21: TMODE and CFB <6:0> Filter Alignment Test Bits
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ML5800
PHYSICAL DIMENSIONS
Pin #1
Notes: 1.) All dimensions are in millimeters (mm) or [Inches] 2.) General tolerances: 0.05 [0.002] 3.) This package meets "Green" Pb-Free requirements and is compliant with the European Union directives WEEE (Waste Electrical and Electronic Equipment) and RoHS (Restriction of the use of certain Hazardous Substances in electrical and electronic equipment). The package pins are finished with 100% matte tin.
Figure 8: 32 Leadless Plastic Chip Carrier (LPCC) Dimensions
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ML5800
WARRANTY
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications. If this document is "Advance", its contents describe a Micro Linear product that is currently under development. All detailed specifications including pinouts and electrical specifications may be changed without notice. If this document is "Preliminary", its contents are based on early silicon measurements. Typical data is representative of the product but is subject to change without notice. Pinout and mechanical dimensions are final. Preliminary documents supersede all Advance documents and all previous Preliminary versions. If this document is "Final", its contents are based on a characterized product, and it is believed to be accurate at the time of publication. Final Data Sheets supersede all previously published versions. (c) 2006 Micro Linear Corporation. All rights reserved. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
cQ
Micro Linear Corporation 2050 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com
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